In an MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a bulk substrate, performances such as short channel characteristics or uniformity of a threshold voltage, etc., are lowered due to its miniaturization, and power consumption tends to increase.
On the other hand, a MISFET formed on an SOI substrate on which a BOX (Buried Oxide) layer serving as a buried oxide film and an SOI (Silicon On Insulator) layer serving as a semiconductor layer are formed on a base body as a bulk substrate is more excellent in performances such as the short channel characteristics or the uniformity of a threshold voltage than the MISFET on the bulk substrate even when being miniaturized, and is also advantageous in achieving low power consumption. Moreover, the MISFET formed on an SOI substrate is referred to as an MISFET on a thin film BOX-SOI, that is, an SOTB (Silicon On Thin Buried oxide)-MISFET.
As a semiconductor device on which such an SOTB-MISFET is mounted, a semiconductor device on which a non-volatile memory is mounted together is cited. As the non-volatile memory, non-volatile memories using an MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film or an SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) film as the charge storage film are cited.
Japanese Patent Application Laid-open Publication No. 2014-232810 (Patent Document 1) discloses a technique of a semiconductor device in which a memory cell using the MONOS film is formed in an SOI region of an SOI substrate. Japanese Patent Application Laid-open Publication No. 2006-310860 (Patent Document 2) discloses a technique of a flash memory including a flash block formed on an SOI substrate and a body electrode formed in a lower surface of an SOI substrate.
Japanese Patent Application Laid-Open Publication (Translation of PCT Application) No. 2002-520807 (Patent Document 3) discloses a technique of a non-volatile semiconductor device in which a memory transistor includes an SONOS tunnel metal insulating semiconductor field effect transistor. Japanese Patent Application Laid-open Publication No. 2007-234861 (Patent Document 4) discloses a technique of a method of manufacturing a semiconductor device in which in, a first MISFET is formed on a first region of a semiconductor substrate and a second MISFET is formed on a second region of the semiconductor substrate.